1. Technical Field
Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to processors to manipulate operation masks in response to instructions.
2. Background Information
Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, instead of a scalar instruction operating on only one data element or pair of data elements, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements, or multiple pairs of data elements, simultaneously and/or in parallel. For example, multiple data elements may be packed within one register or memory location as packed data or vector data. In packed data, the bits of the register or other storage location may be logically divided into a sequence of multiple generally fixed-sized data elements. Each of the data elements may represent an individual piece of data that is stored along with other data elements often having the same size. For example, a 256-bit packed data register may have four 64-bit data elements, eight 32-bit data elements, sixteen 16-bit data elements, or thirty-two 8-bit data elements. Each of the packed data elements may represent a separate individual piece of data (e.g., a color of a pixel, a floating point value, etc.) that may be operated on separately or independently of the others. The processor may have parallel execution hardware responsive to the packed or SIMD instruction to perform the multiple operations simultaneously or in parallel. Such SIMD architectures generally help to significantly improve processing speed.